This invention relates to a top gate amorphous silicon thin-film transistor and a method for producing the same. More particularly, the invention relates to a method in which a self-aligned gate is produced through the use of a laser annealing process. These thin-film transistors are suitable for use in flat panel display devices, for example active-matrix liquid-crystal displays, or in other large-area electronic devices.
Various methods have been proposed for defining self-aligned gate structures in top gate thin-film transistors. In some of these methods, the gate conductor has a width which is smaller than the spacing between the underlying source and drain electrodes. This provides some freedom in the positioning of an insulated gate structure over the silicon body of the transistor. Various processes have been proposed for treating the silicon body of the transistor in those areas between the channel region (beneath the gate) and the source and drain electrodes. This is required to reduce the resistance of the silicon layer in regions other than the channel area of the transistor.
The use of the gate electrode in this process results in a self-aligned structure. One proposed method for reducing this resistance is by doping and laser annealing of the silicon layer on either side of the channel area of the transistor, using the insulated gate structure as a mask to protect the channel area. EP 0691688 discloses a method of manufacturing a top gate thin-film transistor using laser annealing and doping of the silicon layer to reduce the contact resistance to the source and drain electrodes.
The method disclosed in EP 0691688 will be described with reference to FIG. 1.
The transistor is formed on a glass substrate 2. An insulation film 4 overlies the glass substrate to provide a more uniform surface than that of the substrate 2. Metallic source and drain electrodes 6 and 8 are formed over the insulation film 4. These electrodes may be formed of, for example, ITO (indium tin oxide), Molybdenum or a Molybdenum alloy. The source and drain electrode 6, 8 are spaced apart, and the silicon body of the transistor fills this spacing, as will be described below.
The entire face of the substrate is treated with a plasma to diffuse dopant atoms 10 into the surface. These dopant atoms are employed to reduce the resistance of the silicon body of the transistor in regions other than the channel area of the transistor, and also provide a good, low resistance contact between the source and drain electrodes 6 and 8 and the silicon body 12.
An amorphous silicon semi-conductor layer 12 covers the spacing between the source and drain electrode 6, 8 and also partially overlies those electrodes as shown in FIG. 1. Subsequently, a gate insulation film 14 and a gate conductor layer 16 are provided, and the gate conductor layer 16 is patterned to define the gate electrode as shown in FIG. 1.
Subsequent laser irradiation 18 causes the dopant atoms 10 to diffuse into the semi-conductor layer 12. The gate electrode 16 acts as a shield so that this diffusion process is inhibited in the channel area of the transistor. The laser treatment also causes the amorphous silicon 12 to melt, and during subsequent cooling the silicon becomes crystallized to form doped polysilicon source and drain regions 12a, 12b, thereby reducing the resistance between the source and drain electrode 6, 8 and the channel area 12c of the transistor. It is desirable that there is no high-resistance undoped semi-conductor material which is not also covered by the gate 16, since this increases the ON-resistance of the transistor. The laser annealing and doping as described in EP 0691688 therefore reduces the ON-resistance, to improve the response characteristics of the transistor. Furthermore, the use of a gate conductor 16 having a width less than the spacing between the source and drain electrode 6, 8 assists in reducing the parasitic capacitances within the transistor structure, as can be seen from the near-perfect alignment of the edge of the source and drain regions 12a and 12b to the respective edges of the gate 16, due to the shadowing of the laser irradiation by the gate 16.
A problem with the method described above is that the laser annealing of the semi-conductor layer 12, to form polysilicon source and drain regions 12a, 12b, may be unsuccessful in causing crystallization throughout the full depth of the semi-conductor layer 12. In particular, a portion of each of the source and drain regions 12a, 12b overlies the source or drain electrodes 6, 8, whereas another portion overlies the insulating film 4. The different thermal properties of the underlying layers influence the melting and recrystallization process of the silicon. It has been found that the metal source and drain electrodes 6, 8, which have large thermal mass, retard the progression of the melt interface in those regions, when compared to the progression of the melt interface towards the insulating film 4. The thermal energy which flows into the metal of the electrodes 6,8 depends largely on the thermal capacity, for short times such as those used for laser irradiation. The thermal capacity is proportional to the specific heat times the density, and is 2-3 greater for Mo than for Si.
As a result, after the laser annealing process, an amorphous layer of silicon may still remain over the surface of the source and drain electrodes 6, 8 giving increased resistance to the channel 12c and thereby defeating the purpose of the laser crystallization process. One solution to this problem would be to prolong the laser annealing process to ensure that the full thickness of the semi-conductor layer 12 is melted before allowing cooling to take place. However, this may result in damage to the underlying layers for those areas of the silicon layer where the melt interface progresses most rapidly.
It has also been found that the amorphous silicon may peel away from the source and drain electrodes 6, 8 during the laser annealing process. This is particularly found for ITO source and drain electrodes.
According to the invention, there is provided a method of producing a top gate thin-film transistor, comprising the steps of:
forming doped silicon source and drain regions on an insulating substrate;
subjecting the face of the substrate on which the source and drain regions are formed to plasma treatment to form a doped surface layer having impurity atoms diffused therein;
forming an amorphous silicon layer on the doped surface layer over at least the spacing between the source and drain regions;
forming an insulated gate structure over the amorphous silicon layer comprising a gate insulator and an upper gate conductor, the gate conductor being patterned to be narrower than the spacing between the source and drain regions;
laser annealing areas of the amorphous silicon layer not shielded by the gate conductor to form polysilicon portions having the impurities diffused therein.
In the method of the invention, doped silicon source and drain regions underlie the silicon layer to be crystallized using the laser annealing process. It has been found that the laser annealing process can then result in crystallization of the full thickness of the amorphous silicon layer. This results from the similar thermal properties of the doped source and drain regions and the silicon layer defining the main body of the transistor.
The method preferably additionally comprises the step of forming source and drain electrodes with which contact is made by the source and drain regions. The source and drain regions thus provide an intermediate layer between the conventional source and drain electrodes, which are preferably metallic, and the polycrystalline layer which is formed by the laser annealing process. Preferably, the source and drain electrodes are formed on the insulating substrate before the formation of the source and drain regions, the source and drain regions at least partially overlying the source and drain electrodes.
The invention also provides a top gate thin-film transistor comprising:
doped silicon source and drain regions defined from a first silicon layer over an insulating substrate;
a second silicon layer overlying the first silicon layer and extending between the source and drain regions, source and drain portions of the second silicon layer which contact the source and drain regions comprising doped polysilicon and a channel portion of the second silicon layer between the source and drain portions, which is narrower than the spacing between the source and drain regions, comprising substantially undoped amorphous silicon; and
an insulated gate structure over the channel portion of the second silicon layer.
The source and drain regions may comprise doped polysilicon.